Dynamic Random Access Memory (DRAM) devices have memory cells with a field effect transistor and a capacitor. High capacity DRAM devices typically use a non-planar capacitor structure, such as a trench capacitor or a stacked capacitor. Although non-planar capacitor structures typically require more masking, depositing, and etching processes than planar capacitor structures, most high capacity DRAM devices use non-planar capacitors. In both non-planar and planar capacitors, a metal-insulator-metal (MIM) structure provides higher capacitance to enable higher density devices. Typical MIM capacitors have top and bottom conducting layers separated by a dielectric layer. The top and bottom conducting layers, which are also referred to as electrodes or plates, can be composed of the same material or different materials. One aspect of fabricating MIM capacitors is providing a dielectric layer having a high dielectric constant so that more charge can be stored in a capacitor for a given thickness of the dielectric layer. Another parameter of fabricating MIM capacitors is providing a sufficiently thick dielectric layer to mitigate or eliminate current leakage. In general, it is desirable to use a dielectric layer with a high dielectric constant to enable small capacitors to store the same amount of charge with low leakage levels as relatively large capacitors.
Tantalum oxide is one promising material for forming dielectric layers in MIM capacitors. In existing capacitors, a first electrode of ruthenium is deposited directly onto a plug located over diffusion regions. A dielectric layer of amorphous tantalum oxide is then deposited onto the ruthenium layer using a vapor deposition process at 300-450° C. The amorphous tantalum oxide has a dielectric constant of about 18-25. To increase the dielectric constant of the tantalum oxide layer to about 40-50, it is subsequently crystallized using a separate high temperature process above 300° C. (e.g., typically between 600-800° C.). Such additional high temperature processing to crystallize the tantalum oxide, however, may impact the thermal budget of manufacturing the microelectronic devices. For example, high temperature processes are typically avoided to prevent destabilization of the films, diffusion of dopants/implants, and generation of undesirable stresses in film stacks. High temperature annealing processes are also avoided because they would require additional time-consuming procedures that must be integrated into the fabrication process. Therefore, it would be desirable to form a tantalum oxide dielectric layer with a high dielectric constant without annealing the tantalum oxide at a high temperature in a separate process after it has been deposited.